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Neural networks and systolic array design/ David Zhang and Sankar K. Pal eds.

Contributor(s): Material type: TextTextLanguage: English Series: Series in Machine Perception and Artificial Intelligence ; Vol. 49Publication details: New Jersey: World Scientific, 2002Description: xiv,405 pages, diags. 23 cmISBN:
  • 9810248407
Subject(s): DDC classification:
  • 006.32 Z63 23
Contents:
Preface -- Chapter 1. Neural networks and systolic arrays: models and integration -- Chapter 2. Systolic array methodology for a neural model to solve the mixture problem -- Chapter 3. Morphological endmember identification and its systolic array design -- Chapter 4. MANTRA I: A Systolic array for neural computation -- Chapter 5. Mixed -signal neuro-fuzzy processor implementations: sequential architectures and circuit-level description -- Chapter 6. CMAC neural networks and systolic implementation -- Chapter 7 Quadrant interlocking factorization on systolic and wavefront array processors -- Chapter 8. Systolic S.O.M. Neural network for hyperspectral image classification -- Chapter 9. Optimizing and learning algorithm for feedforward neural networks and its implementation by systolic array -- Chapter 10. Parallel ANN architecture for fuzzy patterns -- Chapter 11. Pipelined systolic arrays for time-delay neural networks -- Chapter 12. An Integrated intelligent classification engine for biosignal engineering -- Chapter 13. Multiplierless designs for artifical neural networks -- Chapter 14. A VLSI system for intelligent decision making in real-time -- Chapter 15. Reconfigurable hardware systolic array for real-time compartmental modeling of large-scale artificial nervous systems -- Chapter 16. Implementing and mapping ANNs on reconfigurable mesh massively parallel architectures
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Includes bibliographical references and index

Preface -- Chapter 1. Neural networks and systolic arrays: models and integration -- Chapter 2. Systolic array methodology for a neural model to solve the mixture problem -- Chapter 3. Morphological endmember identification and its systolic array design -- Chapter 4. MANTRA I: A Systolic array for neural computation -- Chapter 5. Mixed -signal neuro-fuzzy processor implementations: sequential architectures and circuit-level description -- Chapter 6. CMAC neural networks and systolic implementation -- Chapter 7 Quadrant interlocking factorization on systolic and wavefront array processors -- Chapter 8. Systolic S.O.M. Neural network for hyperspectral image classification -- Chapter 9. Optimizing and learning algorithm for feedforward neural networks and its implementation by systolic array -- Chapter 10. Parallel ANN architecture for fuzzy patterns -- Chapter 11. Pipelined systolic arrays for time-delay neural networks -- Chapter 12. An Integrated intelligent classification engine for biosignal engineering -- Chapter 13. Multiplierless designs for artifical neural networks -- Chapter 14. A VLSI system for intelligent decision making in real-time -- Chapter 15. Reconfigurable hardware systolic array for real-time compartmental modeling of large-scale artificial nervous systems -- Chapter 16. Implementing and mapping ANNs on reconfigurable mesh massively parallel architectures

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