TY  - BOOK
AU  - Saxena Prashant
AU  - Sapatnekar Sachin S
AU  - Shelar Rupesh S
TI  - Routing congestion in VLSI circuits: estimation and optimization
SN  - 978-0-387-30037-5
U1  - 621.395 
PY  - 2007///
CY  - New York
PB  - Springer-Verlag
KW  - Integrated circuits
KW  - Very large scale integration
N2  - This book provides the reader with a complete understanding of the root causes of routing congestion in present-day and future VLSI circuits, available techniques for estimating and optimizing this congestion, and a critical analysis of the accuracy and
ER  -